The present invention relates in general to integrated circuits and, more particularly, to multilevel interconnections on integrated circuits.
Many semiconductor devices are fabricated using more than one layer of interconnect metallization. For example, integrated circuits commonly have multiple interconnect layers, wherein an underlying interconnect layer is separated from a subsequent interconnect layer by a dielectric layer formed between them. Via openings are made in the dielectric layer to expose the underlying interconnect layer so it can be contacted by the subsequent interconnect layer.
Multilevel metallization structures typically use landed vias to provide contact between metal layers. A landed via is one in which the underlying metal trace is flared out or "dog-boned" around the via such that even if the via is misaligned it will lie completely over the underlying metal trace, whereas a nonlanded via is one which lies over an edge of an underlying metal trace. Landed vias are commonly used because the metal region acts as a natural etch stop to the via etch process. However, landed vias have a disadvantage of reducing the interconnect density because the "dog-bone" feature, rather than the metal line itself, defines the minimum space between lines.
Nonlanded vias increase interconnect density but they are more difficult to fabricate because the metal trace does not act as an etch stop. As a result, a more complex via process is used in order to prevent voids from being formed in the dielectric layer when the via openings are overetched. Such voids often result in reliability failures in the integrated circuit. A previously known method fills the voids using a complex chemical vapor deposition process. However, this method requires multiple processing steps which adds substantial cost to the fabrication of the integrated circuit. Another known method uses titanium as a wetting agent to assist in the extrusion of metal from a subsequent interconnect layer to fill the voids. However, this method requires special equipment which also increases the integrated circuit manufacturing cost.
Hence, there is a need for a method for forming via openings which does not reduce the density of the underlying metal layer by using a flared metal trace to provide an etch stop for the via etch process. It would be a benefit if the via opening could be formed at low cost using a simple process which does not require special equipment.